Automated Reliability Optimization for SRAM-based FPGAs

Today’s most densely integrated Field Programmable Gate Arrays (FPGAs) store their configuration in integrated volatile SRAM cells and thereby offer virtually limitless reconfigurability. However, randomly occurring bit flips in an SRAM-based FPGA’s configuration memory can alter the implemented circuit. Furthermore, bit flips in user-defined storage elements such as flip-flops and block memory can corrupt the design’s state. Both effects may compromise system functionality, making SRAM-based FPGAs especially vulnerable to bit flips. As a mitigation measure, on-chip spatial redundancy is often introduced.
This, however, increases FPGA resource usage and thereby system cost. Selectively protecting the design parts that are most vulnerable to bit flips allows to balance cost and reliability.
This requires identifying especially vulnerable parts of the design to co-optimize a design’s bit-flip resilience with system cost. Existing reliability prediction approaches for FPGA designs often focus on logic resources, overlooking the significant and harder-to-predict effects of interconnect bit flips. Additionally, they do not account for process, voltage, and temperature variations on the outcome of configuration memory bit flips. These gaps in fault modeling limit current design-space exploration methods, preventing them from evaluating the impact of fault mitigation measures on bit-level reliability.
This dissertation addresses these challenges with the following contributions.

1. This work provides an in-depth analysis of configuration memory bit flips in SRAM-based FPGAs. Based on this analysis, it develops and validates criticality prediction models to classify bitstream bits as benign or malignant when flipped. This reduced the need for time-consuming fault injection experiments by 60% to 98% with minimal false negatives in four case studies. In this course, this dissertation provides the first systematic study of how chip temperature and operating voltage influence configuration-level fault injection outcomes in FPGAs, which revealed significant inter- and intra-device variations in bit flip effects.

2. Based on the fault modeling work discussed above, an automated module-based design-space exploration approach for partial redundancy insertion is proposed. It co-optimizes FPGA resource usage and vulnerability to single-bit flips by encoding the module selection problem for genetic algorithms. In this course, it defines fitness metrics based on cost and vulnerability. Evaluated on six case-study designs, the approach generates Pareto-optimal partially redundant design variants, improving the cost-effectiveness of solutions by 13 to 59 percentage points compared to random starting sets. This method provides a diverse range of design variants along the cost-reliability trade-off. This enables the designer to select a variant that best fulfills the application’s, mission’s, or mission phase’s requirements.

3. A profiling approach is proposed for FPGA designs generated by high-level synthesis. The approach aims at identifying critical user-defined storage elements by profiling the design’s memory access patterns at the high-level language or intermediate representation level. Fault injection evaluations of case-study designs based on well-known benchmarks revealed a potential link between this memory access behavior and the in-hardware vulnerability of storage elements. This enables cost-effective design variants with partial bit-flip protection for user-defined storage elements. Furthermore, this high-level analysis may guide the design-space exploration process mentioned above, accelerating convergence.

In summary, this dissertation contributes multiple methods for automating reliability improvements for SRAM-based FPGA designs.
These methods are based on empirical analyses of FPGA vulnerabilities and address effects previously overlooked in existing research.