TIMEA: Time-triggered message-based multicore architecture for AUTOSAR

Multi-Processors System-on-a-Chips (MPSoCs) are becoming a preferred option for the development of embedded system applications. They provide the possibility to execute different software components in parallel on different cores. In the last years several MPSoC architectures have been developed for specific application domains (e.g., by intel, powerpc, etc). However, commercial MPSoCs are the cause of major concern to certification authorities. The paradigm of message-based Networks-on-a-Chip (NoC) with support for time-triggered communication provides significant advantages with respect to temporal predictability, fault isolation and energy efficiency in comparison to the common shared memory approaches implemented for the development of multicore systems. Therefore predictable multicore platforms (e.g., COMPSOC, GENESYS MPSoC) provide message-based on-chip networks as a solution.
At present, in the automotive domain, multicore processors are deployed that use the paradigm of shared memory for the interaction between the cores. The AUTOSAR (Automotive Open System Architecture) standard introduces a multicore version of its Electronic Control Unit (ECU) software architecture since the version 4, defining a multicore operating system that controls the execution of AUTOSAR Software Components (SWCs) allocated to different cores with a shared memory for the inter-core communication. However, AUTOSAR does not provide any approach for the mapping of its ECU software architecture to a NoC-based MPSoC.
In order to combine the benefits of NoC-based MPSoCs with the AUTOSAR standard, this dissertation presents a novel system architecture which maps the AUTOSAR single-core ECU software architecture to a message-based multicore platform. The so-called TIMEA (TIme-triggered MEssage-based multicore platform for AUTOSAR) defines a message-based NoC as the only physical medium for the communication between the cores and introduces autonomous application cores which function as AUTOSAR Micro-ECUs (μECUs) on the MPSoC. Each μECU acts as a unit of abstraction where the SWCs are provided with a Run-Time Environment (RTE) and a lightweight implementation of the AUTOSAR Basic Software (BSW), exploiting the advantages of message-based NoC in contrast to a shared memory approach (e.g., fault isolation, temporal predictability).
Furthermore, computationally expensive functionality of the basic software is delegated to system cores, which serve as hardware accelerators for the application cores. TIMEA supports fault-tolerance mechanisms by the integration of new BSW modules for health monitoring services and proxy functionalities for accessing the dedicated system cores offering SWC redundancy at the core level and at the MPSoC level.
TIMEA was prototypically implemented and evaluated using a simulation framework. The simulation framework consists of an AUTOSAR simulator and on-chip simulator for the implementation of the models and algorithms. Automotive use cases based on an anti-lock braking system and a light indicator system served for the evaluation.
The obtained results demonstrate a better fault isolation for the AUTOSAR system due to the use of an on chip network for the inter-core communication. TIMEA supports stringent temporal guarantees for the SWC interaction between different cores. Moreover, the reliability of the AUTOSAR multicore system was improved considerably. Faults at the SWC level and at the core level are detected and recovery solutions based on SWC redundancy are exploited. Finally, the proposed architecture supports, for the first time, an AUTOSAR multicore platform with SWC communication through a message-based NoC.